1. Field of Invention
The present invention relates to a method of fabricating a semiconductor integrated circuit. More particularly, the present invention relates to a method of fabricating an integrated circuit having a layered structure.
2. Description of Related Art
In general, an integrated circuit (IC) that contains a large number of junction devices such as diodes, well resistors, N.sup.30 resistors, bipolar junction transistors (BJTs) and so on needs lots of wafer area to accommodate these devices. Hence, the level of integration for these devices is greatly reduced.
Furthermore, when these junction devices integrate with metal-oxide-semiconductor (MOS) transistors in the same silicon wafer, serious latch-up problems and difficulties in precisely controlling the operating voltage may occur if the distance of isolation between the devices is insufficient.
In light of the foregoing, there is a need to provide an improved method of integrating junction devices with MOS transistors.